1. Field of the Invention
The present invention relates to semiconductor devices and a module loaded with the same and more particularly to semiconductor devices that are effective when they are mutually mounted on both sides of a substrate and a module loaded with the same.
2. Description of the Related Art
Semiconductor devices, especially semiconductor memories represented by DRAMs, are often mounted on both sides, not only on one side, of a substrate.
Examples of them are what are called a dual in-line memory module (DIMM) and a Rambus in-line Memory module (RIMM).
As is well known, in the DIMM or the RIMM a plurality of synchronous DRAMs (SDRAMs) or Rambus DRAMs (RDRAMs) are mounted on both sides of a substrate. Thus, for example 16 RDRAMs are mounted on one substrate to be used as a memory module having a memory capacity 16 times as large as that of a single RDRAM.
However, in such a module, there arise the following problems that occur hardly in a module (for example, a single in-line memory module (SIMM)) in which semiconductor devices are mounted only on its one side. This will be illustrated by referring to FIG. 5 and FIG. 6.
In FIG. 5 showing a part of a memory module loaded with a plurality of RDRAMs on a substrate 70, only three RDRAMs 72, 74 and 76, out of a plurality of them, are illustrated. On the substrate 70 a plurality of wirings are formed as well. In FIG. 5, however, only a wiring 78 connected to the terminals P of the RDRAMs 72, 74 and 76 is shown. Here, the RDRAMs 72, 74 and 76 are chip scale packages (CSPs) with identical configuration in which RDRAM chips with identical constitution are respectively implemented.
When a signal (for example, an address signal or one of various kinds of control signal) is input to terminals 72-P, 74-P and 76-P of the RDRAMs 72, 74 and 76 through the wiring 78, if it is assumed that the signal is supplied in the direction of an arrow in FIG. 5, the signal arrives first at the terminal 72-P, next at the terminal 76-P and then at the terminal 74-P. Now terminals 72-Q, 74-Q and 76-Q of the RDRAMs 72, 74 and 76 also receive a prescribed signal through a wiring which is not shown. It is noted that terminals 72-P, 74-P and 76-P of the RDPAMs 72, 74 and 76 transmits the same signal, for example, an address signal. and terminals 72-Q, 74-Q and 76-Q of the RDRAMs 72, 74 and 76 transmits the same signal different from the signals transmitted at that terminals 72-P, 74-P and 76-P, for example, a data signal or a control signal. If it is also assumed that this signal is supplied also in the direction of the arrow in FIG. 5, the signal arrives first at the terminal 72-Q, next at the terminal 76-Q, then at the terminal 74-Q. Namely, although the order of arrival of the signal is the same as that of the signal impressed to the terminals 72-P, 74-P and 76-P, the timing of arrival of the signal is different for each RDRAM. In other words, when a signal to be applied to the terminals P and a signal to be applied to the terminals Q of respective RDRAMs are supplied simultaneously in the direction of the arrow, for the RDRAMs 72 and 74, the timings are such that the signal arrives at the terminals 72-Q and 74-Q after its arrival at the terminals 72-P and 74-P, whereas for the RDRAM 76, the signal arrives at the terminal 76-P after its arrival at the terminal 76-Q.
As in the above, in a module where semiconductor devices are loaded on both sides of the substrate, the arrival timings of the signal are different for the semiconductor devices on one side of the substrate and for the semiconductor devices loaded on the other side of the substrate, which has been a factor for the reduction of the margin in the setup/hold time or the like.
It is to be noted that the problem of shift in the timings occurs not only in a signal supplied to each semiconductor device, but also in a signal output from each semiconductor device.
The above problem can be resolved by packaging semiconductor chips of identical configuration into two kinds of packages having mutually different terminal arrangements, then loading one kind of packages on one side of the substrate, and loading the other kind of packages on the other side of the substrate. Namely, what is needed is to make the terminal arrangement of the packages to be loaded on one side of the substrate to be symmetric with the terminal arrangement of the packages to be loaded on the other side of the substrate. The two kinds of packages are in a relation of the left and right hands, so that when they face with each other, that is, when they are loaded on both sides of the substrate, the terminal positions of both kinds of packages match precisely. The two kinds of packages with such a property are called respectively a normal type and a mirrored type, and the mirrored type package has a terminal arrangement which is the mirror reflection of that of the normal type package. as the name suggests.
The circumstance by which the above problem can be resolved by the use of the normal type and the mirrored type packages will be described by reference to FIG. 6. In FIG. 6, the RDRAMs 72 and 74 are normal type CSPs and the RDRAM 80 is a mirrored type CSP.
As shown in the figure, the arrangement of the terminals P and Q in the RDRAM 80 is opposite to that in the RDRAMs 72 and 74, so that the relation between the arrival times of a signal applied to the terminals 72-P, 74-P and 80-P, and a signal applied to the terminals 72-Q, 74-Q and 80-Q are equal for respective RDRAMs. In other words, for all DRAMs, the signal arrives first at the terminal P, then at the terminal Q after a predetermined time. Accordingly, it is possible to resolve the above problem of reduction in the margin of the setup/hold time or the like that arises when packages with identical terminal arrangement are to be loaded on both sides of the substrate, as shown in FIG. 5.
Since, however, the semiconductor chip to be mounted on the normal type package and on the mirrored type package has identical configuration, for mounting the semiconductor chip on the mirrored type package, the wirings for connecting terminals on the semiconductor chip (internal terminals) to the terminals on the package (external terminals) in the package, has to be made differently from those of the normal type package. For this reason, there may occur a case in which it is impossible to connect an internal terminal on the semiconductor chip to an external terminal on the package depending upon their positional relationship.
In FIG. 7 and FIG. 8 for describing such a situation, a semiconductor device 90-N in FIG. 7 is a normal type package while a semiconductor device 90-M in FIG. 8 is a mirrored type package. Here, the semiconductor devices 90-N and 90-M are CSPs. In FIG. 7, a small square represents a terminal on the semiconductor chip, and a circle represents a terminal of the package. The terminal on the semiconductor chip and the terminal of the package are connected electrically by a tape wiring 98. It should be mentioned that the technique of using a tape wiring for the wiring within the package is one feature of the CSP.
As shown in FIG. 7, signal input terminals 92-A, 92-B and 92-C on the semiconductor chip are connected by the tape wiring 98 to terminals A, B and C, respectively, of the package. a power terminal 94 is connected to a terminal V of the package by the tape wiring 98, and a ground terminal 96 is connected to a terminal G of the package by the tape wiring 98. Besides, NC is a nonconnected terminal which is not used.
When a semiconductor device 90-N with such a terminal arrangement is inverted on the plane of the paper with respect to the line connecting the terminals of 92-B, a semiconductor device 90-M having a terminal arrangement as shown in FIG. 8 is obtained. However, as mentioned in the above, the semiconductor chip itself to be mounted on a normal type package or a mirrored type package has identical configuration, so that there might appear locations at which connection of a terminal on the semiconductor chip and a terminal of the package is impossible.
FIG. 8 is a diagram showing such a situation in which, in the mirrored type package, connections between the terminal 92-A and the terminal A, and the terminal 92-C and the terminal C are impossible. In such a case, the manufacture of a mirrored type package is no longer possible. Nonetheless, if one wants to manufacture such a package, it is necessary to prepare separately semiconductor chips for normal type and for mirrored type, which means the necessity of manufacturing two kinds of semiconductor chips and a large increase in the manufacturing cost.
It is therefore an object of the present invention to resolve the above-mentioned problem and to provide semiconductor devices which facilitate the mounting on the normal type package as well as on a mirrored type package.
It is another object of the present invention to provide a module loaded with such semiconductor devices.
According to this invention, there is provided a semiconductor device equipped with a first and second signal terminals, a control terminal, and a switching means which connects the first signal terminal to a first internal wiring in response to the control terminal being in a first state, connects the first signal terminal to a second internal signal wiring different from the first internal signal wiring in response to the control terminal being in a second state different from the first state, and connects the second signal terminal to the first internal signal wiring.
Moreover, according to this invention, there is provided a semiconductor device equipped with a first and second signal terminals, a control terminal, and a switching means which transmits a signal supplied to the first signal terminal to a first internal signal wiring in response to the control terminal being in a first state, transmits a signal supplied to the first signal terminal to a second internal signal wiring different from the first internal signal wiring in response to the control terminal being in a second state different from the first state, and transmits a signal supplied to the second signal terminal to the first internal signal wiring.
Furthermore, according to this invention, there is provide a semiconductor device equipped with a first and second internal signal terminals, an internal control terminal, a first and second internal signal wirings, a firsts and second external signal terminals, a first and second external power terminals, a switching means which connects the first internal signal terminal to the first internal signal wiring when the internal control terminal is connected to the first external power terminal, connects the first internal signal terminal to the second internal signal wiring when the internal control terminal is connected to the second external power terminal, and connects the second internal signal terminal to the first internal signal wiring, a first external signal wiring which connects the first internal signal terminal to the first external signal terminal, and a second external signal wiring which connects the second internal signal terminal to the second external signal terminal.
Furthermore, according to this invention, there is provided a semiconductor device equipped with a first and second external power terminals, an external signal terminal, a first and second internal signal terminals, an internal control terminal, an internal signal wiring, a first external wiring which connects the first internal signal terminal to the external signal terminal, an element which blocks the connection of the second internal signal terminal and the external signal terminal, a switching means which connects the first internal signal terminal to the internal signal wiring when the internal control terminal and the first external power terminal are connected, and connects the second internal signal terminal to the internal signal wiring when the internal control terminal and the second external power terminal are connected, and a second external wiring which connects the control terminal and the first external power terminal.
In this way, even when the connection between an internal terminal on the semiconductor chip and an external terminal on the package is impossible or difficult, the function of the internal terminal on the semiconductor chip can be switched to the function of another internal terminal by means of the switching means, so that the connection can be made possible or facilitated.
Besides, according to this invention, there is provided a module which is equipped with a first and second semiconductor chips, a normal package mounted with the first semiconductor chip, a mirrored package mounted with the second semiconductor chip, and a substrate having the normal package mounted on one side and the mirrored package mounted on the other side, where each of the first and second semiconductor chips is equipped with a first and second signal terminals, a control terminal, and a switching means which connects the first signal terminal to a first internal signal wiring when the control terminal is connected to a first power supply, connects the first signal terminal to a second internal signal wiring different from the first internal signal wiring when the control terminal is connected to a second power supply different from the first power supply, and connects the second signal terminal to the first internal signal wiring, wherein the control terminal of the first semiconductor chip is connected to the first power supply in the normal package, and the control terminal of the second semiconductor chip is connected to the second power supply in the mirrored package.
Moreover, according to this invention there is provided a module which is equipped With a first and second semiconductor chips each of which is provided with a first and second internal signal terminals, a control terminal, and a switching means which connects the first internal signal terminal to a prescribed internal signal wiring in response to the application of a first voltage to the control terminal, and connects the second internal signal terminal to the prescribed internal signal wiring in response to the application of a second voltage different from the first voltage to the control terminal, a normal package mounted with the first semiconductor chip, a mirrored package mounted with the second semiconductor package, and a substrate loaded with the normal packages on one side and mounted with the mirrored packages on the other side, where the normal package is equipped with a first external power terminal to which is applied the first voltage a first external signal terminal, a means for connecting the first external power terminal and the control terminal of the first semiconductor chip, and a means, for connecting the first external signal terminal to the first internal signal terminal of the first semiconductor chip, and the mirrored package is equipped with a second external power terminal to which is applied the second voltage, a second external signal terminal which corresponds to the first external signal terminal of the normal package, a means for connecting the second external power terminal and the control terminal of the second semiconductor chip, and a means for connecting the second external signal terminal and the second internal signal terminal of the second semiconductor chip.